IS25LE128E-RLLA3:P-TY datasheet(69/197 Pages) ISSI

부품명	IS25LE128E-RLLA3:P-TY

상세설명	SERIAL FLASH MEMORY 133/166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

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IS25LE256E/128E

IS25WE256E/128E

Integrated Silicon Solution, Inc.- www.issi.com

Rev.A9

03/07/2023

Figure 8.6 Fast Read Sequence In QPI Mode (0Bh [EXTADD=1] or 0Ch, 4-byte address)

0Bh/0Ch

CE#

SCK

IO[3:0]

6 Dummy Cycles

4-byte Address

...

Mode 3

Mode 0

31:28

7:4

3:0

Data 1

27:24

15:12 11:8

7:4

3:0

...

Instruction

23:20 19:16

Note: Number of dummy cycles depends on Read Parameter setting. Detailed information in Table 6.11 Read Dummy

Cycles.

8.5 HOLD OPERATION

HOLD# is used in conjunction with CE# to select the device. When the device is selected and a serial sequence is

underway, HOLD# can be used to pause the serial communication with the master device without resetting the

serial sequence. To pause, HOLD# is brought low while the SCK signal is low. To resume serial communication,

HOLD# is brought high while the SCK signal is low (SCK may still toggle during HOLD). Inputs to SI will be ignored

while SO is in the high impedance state, during HOLD.

Note: HOLD is not supported in DTR mode or with QE=1 or when RESET# is selected for the HOLD# or RESET# pin.

Timing graph can be referenced in AC Parameters Figure 9.4.

IS25LE128E-RLLA3:P-TY 데이터시트(PDF) 69 Page - Integrated Silicon Solution, Inc