IS25LE128E-RLLA3:P-TY datasheet(166/197 Pages) ISSI

부품명	IS25LE128E-RLLA3:P-TY

상세설명	SERIAL FLASH MEMORY 133/166MHZ MULTI I/O SPI & QUAD I/O QPI DTR INTERFACE WITH ON-CHIP ECC

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IS25LE256E/128E

IS25WE256E/128E

Integrated Silicon Solution, Inc.- www.issi.com

166

Rev.A9

03/07/2023

8.59 WRITE PPB LOCK BIT OPERATION (WRPLB, A6h)

The Write PPB Lock Bit (WRPLB) command clears the PPB Lock (PPBLK) bit to zero. Before the WRPLB command

can be accepted by the device, a Write Enable (WREN) command must be issued and decoded by the device,

which sets the Write Enable Latch (WEL) in the Status Register to enable any write operations.

The WRPLB command is entered by driving CE# low, followed by the instruction code. CE# must be driven high

after the eighth bit of instruction has been latched in. If not, the WRPLB command is not executed. As soon as CE#

is driven high, the WRPLB operation is initiated. While the WRPLB operation is in progress, the Status Register

may still be read to check the value of the Write In

Progress (WIP) bit. The WIP bit is “1” during the WRPLB

operation, and is “0” when it is completed. When the WRPLB operation is completed, the WEL is set to “0”.

Figure 8.133 Write PPB Lock Bit Sequence In SPI Mode

Instruction = A6h

CE#

SCK

Mode 3

Mode 0

High Impedance

Figure 8.134 Write PPB Lock Bit Sequence In QPI Mode

A6h

CE#

SCK

IO[3:0]

Mode 3

Mode 0

IS25LE128E-RLLA3:P-TY 데이터시트(PDF) 166 Page - Integrated Silicon Solution, Inc