L99LDLH32 datasheet(53/142 Pages) STMICROELECTRONICS

53 / 142 page

DS12879 Rev 6

53/142

L99LDLH32

Communication interface

141

The subsequent data bytes are the data transferred from the Responder device with every

communication to Commander.

Table 14. Global status byte field description

Bit #

Name

Description

GSBN

Global Status Bit Not

This bit is a NOR combination of the remaining bits of this register:

RSTB nor FE2 nor FE1 nor DE nor GW nor FS

6RSTB

Reset Bit

The RSTB indicates a device reset. In case this bit is set, all internal RAM Control and

Configuration Registers are set to default and kept in that state until the bit is cleared. Any

valid unicast frame requiring GSB in the response frame clears the Reset Bit after

Responder sent its response frame. No data can be written to RAM Configuration and

Control Registers as long as Reset Bit is set. Chain Initialization command will be executed,

but will not clear Reset Bit.

Not used

4FE2

Functional Error 2

The FE2 indicates the logical OR combination of the following errors:

Any Output Channel exceeding short circuit threshold (when enabled): SHT_CHx, or

Any Output Channel in open load: OL_CHx, or

Any Output Channel in short circuit with GND: OUT_SHT_GND_CHx

3FE1

Functional Error 1

The FE1 reports the following error:

Thermal Shutdown: TSD

2DE

Device error

The DE indicates the logical OR combination of the following errors:

Short circuit on external NTC: NTC_FAULT, or

Power Good Threshold not reached: PG_NOT_VPRE_REG, or

Supply voltage undervoltage fault: VS_UV, or

Open or Short Circuit Fault on DAC Reference Resistor: DAC_RES_FAULT

1GW

Global warning

The GW is a logical OR combination of warning flags:

Thermal Warning: TW, or

NTC derating active: NTC_DER_ACT

0FS

Fail safe:

The Fail Safe bit is set, when the device operates in Fail Safe / Stand Alone Mode

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