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M41ST85WMH6F 데이터시트(PDF) 12 Page - STMicroelectronics

부품명 M41ST85WMH6F
상세설명  3.0/3.3 V I²C combination serial RTC, NVRAM supervisor and microprocessor supervisor
PDF  43 Pages
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제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
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Operating modes
M41ST85W
12/43
DocID7531 Rev 12
2
Operating modes
The M41ST85W clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 64 bytes
contained in the device can then be accessed sequentially in the following order:
1.
Tenths/hundredths of a second register
2.
Seconds register
3.
Minutes register
4.
Century/hours register
5.
Day register
6.
Date register
7.
Month register
8.
Year register
9.
Control register
10. Watchdog register
11 - 16. Alarm registers
17 - 19. Reserved
20. Square wave register
21 - 64. User RAM
The M41ST85W clock continually monitors VCC for an out-of-tolerance condition. Should
VCC fall below VPFD, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent
erroneous data from being written to the device from a an out-of-tolerance system. When
VCC falls below VSO, the device automatically switches over to the battery and powers down
into an ultralow current mode of operation to conserve battery life. As system power returns
and VCC rises above VSO, the battery is disconnected, and the power supply is switched to
external VCC.
Write protection continues until VCC reaches VPFD(min) plus trec (min).
For more information on battery storage life refer to application note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a bi-
directional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must be
connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
Data transfer may be initiated only when the bus is not busy.
During data transfer, the data line must remain stable whenever the clock line is high.
Changes in the data line, while the clock line is high, will be interpreted as control
signals.



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