M41ST87YSS6TR datasheet(19/54 Pages) STMICROELECTRONICS

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M41ST87W

Operating modes

DocID9497 Rev 11

19/54

2.6.3

Tamper interrupt enable bits (TIE1 and TIE2)

If this bit is set to a logic '1,' the

IRQ/OUTpinwillbeactivatedwhenatampereventoccurs.

This function is also valid in battery backup if the ABE bit (alarm in battery backup) is also

set to '1' (see Figure 15: "Basic tamper detect options").

Note: In order to avoid an inadvertent activation of the

IRQ/OUTpinduetoapriortamper

event, the flag register (0Fh) should be read prior to clearing and again setting the TEBX

bit.

2.6.4

Tamper connect mode bit (TCM1 and TCM2)

This bit indicates whether the position of the external switch selected by the user is in the

normally open (TCMX = '1') or normally closed (TCMX = '0') position (see Figure 14:

"Tamper detect connection options" and Figure 16: "Tamper detect output options").

2.6.5

Tamper polarity mode bits (TPM1 and TPM2)

The state of this bit indicates whether the tamper pin input will be taken high (to VOUT if

TPMX = '1') or low (to VSS if TPMX = '0') to trigger a tamper event (see Figure 14: "Tamper

detect connection options" and Figure 16: "Tamper detect output options").

Figure 14: Tamper detect connection options

Note: These options are summarized in Table 4: "Tamper detection truth table".

If the CLRXEXT bit is set, a second tamper to VOUT (TPM2 = '1') during tCLR will not be

detected.

If the CLRXEXT bit is set, a second tamper to VOUT (TPM2 = '1') will trigger

automatically.

Optional external resistor to VCC allows the user to bypass sampling when power is

“on.”

TPIN

TAMPER HI

(TPM X = 1)

TAMPER LO

(TPM X = 0)

VOUT

(1)

TPIN

NORMAL LY

CLOSED

(TCM X = 0)

NORMAL LY

OPEN

(TCM X = 1)

IV.

II.

III.

TPIN

VOUT

(2)

TCHI/TCLO = 0

TCHI/TCLO = 1

TCHI/TCLO = 0

TCHI/TCLO = 1

VOUT (Int)

VCC

(3)

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