Functional description

HCF4094

4/17

DocID002069 Rev 5

2

Functional description

Figure 2. Logic diagram

Table 3. Truth table

Clock

Output

enable

Strobe

Data

Parallel outputs

Serial outputs

Q1

Qn

QS(1)

1. At the positive clock edge, information on the 7th shift register stage is transferred to the 8th register stage

and the QS output.

Q’S

LX(2)

2. Don’t care

X(2)

OC(3)

3. Open circuit

OC(3)

Q7

No change

LX(2)

X(2)

OC(3)

OC(3)

No change

Q7

HL

X(2)

No change No change

Q7

No change

HH

L

L

Qn-1

Q7

No change

HH

H

H

Qn-1

Q7

No change

H

H

H

No change No change No change

Q7