Applications information

PM8804

14/27

DocID031629 Rev 1

5.3

Delay time and blanking time: DT and BLK pins

The delay between the rising edge of GAT2 and GAT1 waveforms can be set by connecting

a programming resistor RDT between the pins DT and AGND.

The relationship between the delay time and the RDT resistor is:

Equation 2

The same delay time is set between the GAT1 falling edge and the subsequent GAT2 falling

edge.

The useful range for RDT is from 20 k to 390 k. A resistor must always be connected to

this pin, otherwise the device operation will be stopped.

Figure 5. Timing relationship of DT and BLK signals as a function of RDT/RBLK

The blanking time can be set by connecting a resistor RBLK between the pins BLK and

AGND.

Equation 2 is valid as well for blanking time, where resistor RDT is replaced with resistor

RBLK and tdelay with tblanking.

This internal blanking time is introduced to prevent false overcurrent detection on the rising

edge of GAT1 waveform. The masking logic is activated at the turn-on of the primary side

MOSFET for a duration up to 200 ns.

The useful range for RBLK is between 20 k and 390 k.

tdelay ns



0.6 pC

 R

DT k





1.25 V



-------------------------------------------------- 4ns



+

=