VCC

Unused Input

Input

Output

Output

Input

Unused Input

Vcc - V

0

1

2

3

4

5

6

0

1

2

3

4

5

6

D002

TPD

10

SN74LVC2G07

SCES308L – AUGUST 2001 – REVISED MAY 2015

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Copyright © 2001–2015, Texas Instruments Incorporated

Typical Application (continued)

9.2.3 Application Curve

Figure 4. TPD Across VCC at 25°C

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

Recommended Operating Conditions table.

Each VCC pin should have a good bypass capacitor to prevent power disturbance. For devices with a single

supply a 0.1-μF capacitor is recommended and if there are multiple VCC pins then a 0.01-μF or 0.022-μF

capacitor is recommended for each power pin. It is ok to parallel multiple bypass caps to reject different

frequencies of noise. 0.1-μF and 1-μF capacitors are commonly used in parallel. The bypass capacitor should be

installed as close to the power pin as possible for best results.

11 Layout

11.1 Layout Guidelines

When using multiple bit logic devices inputs should not ever float. In many cases, functions or parts of functions

of digital logic devices are unused; for example, when only two inputs of a triple-input AND gate are used or only

3 of the 4 buffer gates are used. Such input pins should not be left unconnected because the undefined voltages

at the outside connections result in undefined operational states. Specified below are the rules that must be

observed under all circumstances. All unused inputs of digital logic devices must be connected to a high or low

bias to prevent them from floating. The logic level that should be applied to any particular unused input depends

on the function of the device. Generally they will be tied to GND or VCC whichever make more sense or is more

convenient.

11.2 Layout Examples

Figure 5. Layout Examples for SN74LVC2G07