ICS8402AYILF datasheet(4/19 Pages) IDT

4 / 19 page

ICS8402I

350MHZ, CRYSTAL-TO-LVCMOS/LVTTL FREQUENCY SYNTHESIZER

IDT™ / ICS™ LVCMOS/LVTTL FREQUENCY SYNTHESIZER

ICS8402AYI REV. A OCTOBER 16, 2007

Table 2. Pin Characteristics

Function Tables

Table 3A. Parallel and Serial Mode Function Table

NOTE:

L = LOW

H = HIGH

X = Don’t care

↑ = Rising edge transition

↓ = Falling edge transition

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

CIN

Input Capacitance

CPD

Power Dissipation Capacitance

(per output)

VDD, VDDO = 3.465V

VDD = 3.465V, VDDO = 2.625V

RPULLUP

Input Pullup Resistor

Ω

RPULLDOWN Input Pulldown Resistor

Ω

ROUT

Output Impedance

VDDO = 3.465V

Ω

VDDO = 2.625V

Ω

Inputs

Conditions

nP_LOAD

S_LOAD

S_CLOCK

S_DATA

Reset. Forces outputs LOW.

Data

Data on M and N inputs passed directly to the M divider

and N output divider. TEST output forced LOW.

↑

Data

Data is latched into input registers and remains loaded

until next LOW transition or until a serial event occurs.

↑

Data

Serial input mode. Shift register is loaded with data on

S_DATA on each rising edge of S_CLOCK.

↑

LData

Contents of the shift register are passed to the

M divider and N output divider.

↓

Data

M divider and N output divider values are latched.

Parallel or serial input do not affect shift registers.

↑

Data

S_DATA passed directly to M divider as it is clocked.

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