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ICS844256BGLF 데이터시트(PDF) 9 Page - Integrated Device Technology |
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ICS844256BGLF 데이터시트(HTML) 9 Page - Integrated Device Technology |
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9 / 16 page ![]() IDT™ / ICS™ LVDS FREQUENCY SYNTHESIZER W/FANOUT BUFFER 9 ICS844256BG REV. B NOVEMBER 19, 2007 ICS844256 FEMTOCLOCKS™ CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER W/INTEGRATED FANOUT BUFFER PRELIMINARY FIGURE 1. POWER SUPPLY FILTERING 10 Ω V DDA 10 μF .01 μF 3.3V .01 μF V DD APPLICATION INFORMATION CRYSTAL INPUT INTERFACE The ICS844256 has been characterized with 18pF parallel resonant crystals. The capacitor values shown in Figure 2 FIGURE 2. CRYSTAL INPUt INTERFACE below were deter mined using an 18pF parallel resonant crystal and were chosen to minimize the ppm error. C1 18p X1 18pF Parallel Crystal C2 22p XTAL_IN XTAL_OUT INPUTS: LVCMOS CONTROL PINS All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1k Ω resistor can be used. RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS OUTPUTS: LVDS Outputs All unused LVDS output pairs can be either left floating or terminated with 100 Ω across. If they are left floating, we recommend that there is no trace attached. POWER SUPPLY FILTERING TECHNIQUES As in any high speed analog circuitry, the power supply pins are vulnerable to random noise. To achieve optimum jitter perfor- mance, power supply isolation is required. The ICS844256 pro- vides separate power supplies to isolate any high switching noise from the outputs to the internal PLL. V DD, VDDA, and VDDO should be individually connected to the power supply plane through vias, and 0.01µF bypass capacitors should be used for each pin. Fig- ure 1 illustrates this for a generic V CC pin and also shows that V DDA requires that an additional10Ω resistor along with a 10µF bypass capacitor be connected to the V DDA pin. |
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