TMDS181RGZRG4 datasheet(39/60 Pages) TI2

39 / 60 page

TMDS181, TMDS181I

www.ti.com

SLASE75D – AUGUST 2015 – REVISED SEPTEMBER 2017

Product Folder Links: TMDS181

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Table 8. RX PATTERN VERIFIER CONTROL/STATUS Register Field Description(1) (continued)

ADDRESS

BITS

DEFAULT

DESCRIPTION

ACCESS

1Ah

7:0

‘h00

BERT_CNT[19:12]. BERT error count. Lane 1

1Bh

7:4

4’b0000

Reserved

3:0

4’b0000

BERT_CNT[23:20]. BERT error count. Lane 1

1Ch

7:0

‘h00

BERT_CNT[31:24]. BERT error count. Lane 2

1Dh

7:4

4’b0000

Reserved

3:0

4’b0000

BERT_CNT[35:32]. BERT error count. Lane 2

1Eh

7:0

‘h00

BERT_CNT[19:12]. BERT error count. Lane 3

7:4

4’b0000

Reserved

1Fh

3:0

‘h00

BERT_CNT[23:20]. BERT error count. Lane 3

20h

1’b0

Power Down Status Bit.

0 – Normal Operation (default)

1 – Device in Power Down Mode

1’b0

Standy Status Bit.

0 – Normal Operation (default)

1 – Device in Standby Mode

5:0

6’b000000

Reserved

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