IS25LEG-RGLA2:P-TY datasheet(168/193 Pages) ISSI

168 / 193 page

IS25LE01GG

IS25WE01GG

Integrated Silicon Solution, Inc.- www.issi.com

168

Rev. A3

10/02/2025

8.66 DATA LEARNING PATTERN (DLP)

The Data Learning Pattern is a preamble, and it can help host controller to determine the phase shift from SCK to

data edges so that controller can capture data at the center of the data eye at high frequency DTR operation.

DLP can be enabled or disabled by setting the bit EB4 of Extended Read register (DLPEN bit).

When enabled, the device drives all IO bus during last 4 dummy cycles immediately before data is output in DTR

operation. (No DLP operation in STR operation). The host must be sure to stop driving the IO bus at least 1 cycle

prior to the time that the memory starts outputting the DLP during dummy cycles. That is why, when using DDR IO

commands with DLP enabled, 5 or more dummy cycles must be selected.

If there are mode bits for AX read operation, still more than 5 clock cycles are required for DLP operation between

last mode bit and first read data.

DLP operation is valid in DTR operation with valid dummy cycles in SPI mode and QPI mode with below command;

FRDTR (Fast Read DTR) command in SPI and QPI mode.

FRDDTR (Fast Read Dual IO DTR) command in SPI mode only

FRQDTR (Fast Read Quad IO DTR) command in SPI and QPI mode

Data Learning Pattern is programmable, and fixed length of 8-bit in DTR operation.

For example, DLP 34h is programmed, then (0011 0100) data will start output from all IOs before data is output

during 4 clock cycles. All IOs will output 0 at the first clock edge, subsequently, all IOs will output 0, the 3rd will

output 1, etc.

The Data Learning Pattern (DLP) resides in an 8-bit Non-Volatile Data Learning Register (NVDLR) as well as an

8-bit Volatile Data Learning Register (VDLR). NVDLR can be programmed with Program NVDLR (PNVDLR 43h)

command, and VDLR can be written by Write VDLR (WRVDLR 4Ah) command. Also DLP register value can be

read out by Data Learning Pattern Read (RDDLP) command. All 3 commands (PNVDLR, WRVDLR, RDDLP) are

valid in SPI mode and QPI mode.

IS25LEG-RGLA2:P-TY 데이터시트(PDF) 168 Page - Integrated Silicon Solution, Inc