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TPD2EUSB30 데이터시트(PDF) 10 Page - Texas Instruments |
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TPD2EUSB30 데이터시트(HTML) 10 Page - Texas Instruments |
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10 / 28 page ![]() 8.2.2 Detailed Design Procedure To begin the design process, some parameters must be decided upon; the designer needs to know the following: • Signal range on all the protected lines • Operating frequency 8.2.2.1 Signal Range on D+, D- Pins The TPD2EUSB30 has 2 pins which support 0 to 5.5 V and the TPD2EUSB30A has 2 pins which support 0 to 3.6 V. 8.2.2.2 Operating Frequency The 0.7 pF (TPD2EUSB30/A typ) line capacitance supports data rates in excess of 5 Gbps. 8.2.3 Application Curves Figure 8-3. Output Eye Diagram Without TPD2EUSB30/A (Figure 8-2 Setup, 5 Gbps Data Rate) Figure 8-4. Output Eye Diagram With the TPD2EUSB30/A (Figure 8-2 Setup, 5 Gbps Data Rate) Figure 8-5. Output Eye Diagram Without the TPD4EUSB30 (5 Gbps Data Rate) Figure 8-6. Output Eye Diagram with the TPD4EUSB30 (5 Gbps Data Rate) TPD2EUSB30, TPD2EUSB30A, TPD4EUSB30 SLVSAC2G – AUGUST 2010 – REVISED JUNE 2021 www.ti.com 10 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated Product Folder Links: TPD2EUSB30 TPD2EUSB30A TPD4EUSB30 |
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