TPS70445PWPR datasheet(29/44 Pages) TI2

29 / 44 page

TPS704xxPWP

(FixedOutputOption)

0.22 F

22 F

0.22 F

250kW

47 F

>2V

<0.7V

>2V

<0.7V

EN1

EN2

EN1

EN2

IN1

IN2

RESET

OUT1

SENSE1

PG1

SENSE2

OUT2

PG2

OUT2

RESET

PG2

OUT1

95%

EN2

EN1

OUT1

OUT2

PG2

PG1

(PG1tiedto

)

RESET

FAULTONV

OUT1

NOTES:A.t :TimeatwhichV

isgreaterthanV

and

islogichigh.

B.Thetimingdiagramisnotdrawntoscale.

UVLO

120ms

TPS70445, TPS70448

TPS70451, TPS70458

TPS70402

www.ti.com

SLVS307F – SEPTEMBER 2000 – REVISED APRIL 2010

Application condition: VIN1 and VIN2 are tied to

same fixed input voltage greater than VUVLO. PG1 is

tied to MR.

EN1 and EN2 are initially high; therefore, both

regulators are off, and PG1 (tied to MR) and PG2 are

at logic low. Since MR is at logic low, RESET is also

at logic low. When EN2 is taken to logic low, VOUT2

turns on. Later, when EN1 is taken to logic low, VOUT1

turns on. When VOUT2 reaches 95% of its regulated

output voltage, PG2 goes to logic high. When VOUT1

reaches 95% of its regulated output voltage, PG1

goes to logic high. When VIN1 is greater than VUVLO

and MR (tied to PG2) is at logic high, RESET is

pulled to logic high after a 120-ms delay. When a

fault on VOUT1 causes it to fall below 95% of its

regulated output voltage, PG1 (tied to MR) goes to

logic low. Since MR is logic low, RESET goes to logic

low. VOUT2 is unaffected.

Figure 40. Timing When There is a Fault on VOUT1

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