TUSB8042A1RGCRSLASHT datasheet(39/64 Pages) TI2

39 / 64 page

8.25 SMBus Device Status and Command Register

Figure 8-24. Register Offset F8h

Bit No.

Reset State

Table 8-25. Bit Descriptions – SMBus Device Status and Command Register

Bit

Field

Type

Description

7:2

RSVD

Reserved. Read only, returns 0 when read.

smbusRst

RSU

SMBus interface reset. This bit loads the registers back to the GRSTz

values. Note, that since this bit can only be set when in SMBus mode

the cfgActive bit is also reset to 1. When the software sets this bit, the

software must reconfigure the registers as necessary.

This bit is set by writing a 1 and is cleared by hardware on completion

of the reset. A write of 0 has no effect.

cfgActive

RCU

Configuration active. This bit indicates that configuration of the

TUSB8042A is currently active. The bit is set by hardware when the

device enters the I2C or SMBus mode. The TUSB8042A shall not

connect on the upstream port while this bit is 1.

When in I2C mode, the bit is cleared by hardware when the

TUSB8042A exits the I2C mode.

When in the SMBus mode, this bit must be cleared by the SMBus host

to exit the configuration mode and allow the upstream port to connect.

The bit is cleared by a writing 1. A write of 0 has no effect.

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TUSB8042A

SLLSF93A – JUNE 2019 – REVISED JANUARY 2025

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