PR

EL

IM

INA

RY

EVB71121

300 to 930MHz Receiver

Evaluation Board Description

39012 71121 01

Page 4 of 18

EVB Description

Rev. 003

Jan/08

1.3

Block Diagram

Fig. 1:

MLX71121 block diagram

The MLX71121 receiver IC consists of the following building blocks:

•

PLL synthesizer (PLL SYNTH) to generate the first and second local oscillator signals LO1 and LO2.

The PLL SYNTH consists of a fully integrated voltage-controlled oscillator (VCO), a distributed feedback

divider chain (N1, N2), a phase-frequency detector (PFD) a charge pump (CP), a loop filter (LF) and a

crystal-based reference oscillator (RO).

•

Two low-noise amplifiers (LNA) for high-sensitivity RF signal reception

•

First mixer (MIX1) for down-conversion of the RF signal to the first IF (intermediate frequency)

•

Second mixer (MIX2) with image rejection for down-conversion from the first to the second IF

•

IF Filter (IFF) with a 1.8MHz center frequency and a 300kHz 3dB bandwidth

•

IF amplifier (IFA) to provide a high voltage gain and an RSSI signal output

•

FSK demodulator (FSK DEMOD)

•

Operational amplifiers OA1 and OA2 for low-pass filtering and data slicing, respectively

•

Positive (PKDET+) and negative (PKDET-) peak detectors

•

Switches SW1 to select between FSK and ASK as well as SW2 to chose between averaging or peak

detection mode.

•

Noise cancellation filter (NCF)

•

Sequencer circuit (SEQ) and biasing (BIAS) circuit

•

Clock output (DIV8)

LNAI1

LNAI2

LNASEL

MIX1

IFA

LO2

LO1

LNA2

LNA1

IFF

RO

VCO

N2

counter

N1

counter

PFD

LF

CP

DIV 8

FSK

DEMOD

PKDET+

PKDET

_

25

4

6

3

VEE

2

VEE

7

1

28

5

8

30

32

TEST

26

RFSEL

31

15

14

24

27

13

12

11

10

9

OA1

16

17

BIAS

SEQ

NCF

OA2

22

19

ASK

FSK

SW1

SW2

100k

100k

DTAO

29

CINT

23

DFO

PDP

PDN

18

20

21

MIX2