Application Information

Operation

The CLC532 is a 2:1 analog multiplexer with high impedance

buffered inputs, and a low distortion, output stage. The

CLC532 employs a closed-loop design, which dramatically

improves distortion performance. The channel SELECT con-

trol

Figure 1 determines which of the two inputs (IN

is present at the OUTPUT. Beyond the basic multiplexer

function, the CLC532 offers compatibility with either TTL or

ECL logic families, as well as adjustable bandwidth.

Digital Interface and Channel SELECT

The CLC532 functions with ECL, TTL and CMOS logic fami-

lies, D

D

ECL level signals,

Figure 2. For TTL or CMOS level SELECT

inputs (

Figure 3), D

incorporates an internal 2300

Ω series isolation resistor for

the D

SELECT requires a resistor input network to prevent satura-

tion of the channel select circuitry. Without this input net-

work, channel SELECT logic levels above 3V will cause

internal junction saturation and slow switching speeds.

Compensation

The CLC532 incorporates compensation nodes that allow

both its bandwidth and its settling time/slew rate to be ad-

justed. Bandwidth and settling time/slew adjustments are

linked, meaning that lowering the bandwidth also lowers

slew rate and lengthens settling time. Proper compensation

is necessary to optimize system performance. Time domain

applications should generally be optimized for lowest RMS

noise at the CLC532 output, while maintaining settling time

and slew rate at adequate levels to meet system needs.

Frequency Domain applications should generally be opti-

mized for maximally flat frequency response.

System Timing Diagram

A

SELECT

B

SWT90

SWT10

90%

10%

TSx

TRx

TRx

SETTLING ERROR

WINDOW

CHANNEL A = +1V

CHANNEL B = - 1V

OS

... where TSx i s TS14 or TSP or TSS,

and TRx i s TRS ro TSL.

OUTPUT

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System Transient Timing Diagram

A

SELECT

B

ST

2ns

~

~

OUTPUT

Channel A = 0V

Channel B = 0V

DS012716-35

5

8

10

6

9

4

3

2

1

7

13

14

12

CHANNEL A

CHANNEL B

CHANNEL

SELECT

DGND

-5. 2V

0.1

µF

2

1

+5V

CLC532

11

0.1

µF

+6.8

µF

+6.8

µF

DS012716-36

FIGURE 1. Standard CLC532 Circuit Configuration

DS012716-37

FIGURE 2. ECL Level Channel SELECT Configuration

DS012716-38

FIGURE 3. TTL/CMOS Level Channel SELECT

Configuration

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