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EN25F80-100VIP 데이터시트(PDF) 7 Page - Eon Silicon Solution Inc.

부품명 EN25F80-100VIP
상세설명  8 Megabit Serial Flash Memory with 4Kbytes Uniform Sector
PDF  32 Pages
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제조업체  EON [Eon Silicon Solution Inc.]
홈페이지  http://www.essi.com.tw
Logo EON - Eon Silicon Solution Inc.

EN25F80-100VIP 데이터시트(HTML) 7 Page - Eon Silicon Solution Inc.

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This Data Sheet may be revised by subsequent versions
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
7
EN25F80
Rev. E, Issue Date: 2007/11/23
TABLE 3. Protected Area Sizes Sector Organization
Status Register
Content
Memory Content
BP2
Bit
BP1
Bit
BP0
Bit
Protect Blocks
Addresses
Density(KB)
Portion
1
1
1
All
000000h-0FFFFFh
1024KB
All
1
1
0
All
000000h-0FFFFFh
1024KB
All
1
0
1
All
000000h-0FFFFFh
1024KB
All
1
0
0
8 to 15
080000h-0FFFFFh
512KB
Upper 1/2
0
1
1
12 to 15
0C0000h-0FFFFFh
256KB
Upper 1/4
0
1
0
14 to 15
0E0000h-0FFFFFh
128KB
Upper 1/8
0
0
1
15
0F0000h-0FFFFFh
64KB
Upper 1/16
0
0
0
None
None
None
None
Hold Function
The Hold (HOLD) signal is used to pause any serial communications with the device without reset-
ting the clocking sequence. However, taking this signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold
condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial
Clock (CLK) being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides
with Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts af-
ter Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock
(CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in
Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of
the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the
moment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is necessary to
drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from
going back to the Hold condition.
Figure 4. Hold Condition Waveform



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