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2.6

ADR5: GIEN Global Interrupt Enable Register

Figure 21.

2.7

ADR6: IFR Interrupt Flag Register

Figure 22.

Except ESPI all bits in this register are maskable in GIEN. Any masked bit will force NINT low until the register

content is reset (either explicitly or by SPI ‘clear register).

EOVT

EEW

EUV

IRES

ISET

ECW

EWW

EIFW

D7

D0

Enable Identifier

based wakeup / Interrupt

Enable Wakeup,/ Interrupt

via Watchdog

Enable CAN

wakeup / Interrupt

Enable Wakeup / Interrupt

via edge on WAKE

Enable Interrupt

upon CAN error

recovery

Enable Interrupt

upon CAN error

detection

Enable Interrupt

upon Overtemp.

Warning

Enable

Interrupt

upon VS / VREG

Undervoltage

D11

D0

ESPI

ISET

IRES

UV23

WKIF

WKW

WKC

WKE

OVT3

OVT2

OVT1

UVVS

VS < 7.2V

detected

Overtemperature

Warning level reached

OVT1 : T(V1) > 140degC

OVT2 : T(V2) > 140degC

OVT3 : T(V3) > 140degC

Signal edge

on WAKE

detected

Wakeup condition

via CAN detected

Watchdog timeout

detected

Identifier passed

CAN ID-Filter

Reserved bit (‘RES’) has to be written as ‘0’.

CRC- / Format

Error or SCLK-

Timeout detected

by SPI (non maskable)

CAN Linefailure

detected (ISET)

removed (IRES)

V2 or V3

Undervoltage