L6238 datasheet(16/35 Pages) STMICROELECTRONICS

16 / 35 page

3) Phase Lock - After a brief settling time, typi-

cally 1-2 seconds after spin-up, the counters will

alternately count up and down as required to

maintain the phase difference to be as close to

minimum as possible. The counter outputs at this

time should be ”hovering” around 10000000.

The outputs of the two DACs are sent to latches

that store the digital representation of the meas-

ured phase error. This information is then bussed

to the DACs.

4.3 Coarse/Fine DACs

Two DACs are used to convert the digital phase

error information into an analog voltage that can

be used to command the output driver’s current.

In figure 12, the two 8-bit digital error signals are

used to switch in 256 possible voltages derived

from a precision Band-Gap reference. The same

resistor ladder string is used for the Coarse and

Fine DACs. The outputs of the DACS are then

sent to buffer stages and added together via a

summing amplifier.

4.4 Transfer Functions

Figure 13 represent the Output Voltage vs Phase

Error for the Coarse and Fine DACs depicting the

resolution that is achievable.

Table 2 shows examples of the resolution of both

Figure 12: Coarse and Fine DAC’s.

Table 2

Fsystem

Clock

Fcoarse

Phase LSB

Coarse

(Range)

Coarse

Ffine

Phase LSB

Fine

(Range)

Fine

8MHz

15.6KHz

64.1

µs

16.3ms

1.0MHz

1.0

µs

255

µs

10MHz

19.5KHz

51.3

µs

13.1ms

1.25MHz

800ns

204

µs

12MHz

23.4KHz

42.7

µs

10.9ms

1.5MHz

667ns

170

µs

L6238

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