W256

Rev 1.0, November 25, 2006

Page 6 of 7

Figure 1 shows the differential clock directly terminated by a

120

resistor.

Layout Example Single Voltage

)

)

Receiver

60

60

Device

Under

Test

Figure 1. Differential Signal Using Direct Termination Resistor

Out

Out

VTR

VCP

FB

+3.3V Supply or 2.5V Supply

C2

10 F

0.005 F

G

G

VDD

C1

28

27

26

25

24

23

22

21

20

18

1

2

3

4

5

6

7

8

9

10

11

12

13

14

19

17

16

15

G = VIA to GND plane layer

V =VIA to respective supply plane layer

Note: Each supply plane or strip should have a ferrite bead and capacitors

Cermaic Caps C1 = 10–22 µF

C2 = 0.005 µF

FB = Dale ILB1206 – 300 (300

@ 100 MHz)

All bypass caps = 0.1 F ceramic

G

V

G

V

G

V

G

V

G

V

G

G

G

G

G

G

G

G

G