NXP Semiconductors

PCA9537

4-bit I2C-bus and SMBus low power I/O port with interrupt and reset

tSP

tBUF

tHD;STA

P

P

S

tLOW

tr

tHD;DAT

tf

tHIGH

tSU;DAT

tSU;STA

Sr

tHD;STA

tSU;STO

SDA

SCL

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0.7 × VDD

0.3 × VDD

0.7 × VDD

0.3 × VDD

Figure 12. Definition of timing

SCL

SDA

tHD;STA

tSU;DAT

tHD;DAT

tf

tBUF

tSU;STA

tLOW tHIGH

tVD;ACK

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tSU;STO

protocol

START

condition

(S)

bit 7

MSB

(A7)

bit 6

(A6)

bit 1

(D1)

bit 0

(D0)

1 / fSCL

tr

tVD;DAT

acknowledge

(A)

STOP

condition

(P)

0.3 × VDD

0.7 × VDD

0.3 × VDD

0.7 × VDD

Rise and fall times refer to VIL and VIH.

Figure 13. I2C-bus timing diagram

SDA

SCL

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trst

50 %

30 %

50 %

50 %

50 %

trec(rst)

tw(rst)

RESET

IOn

after reset,

I/Os reconfigured

as inputs

START

trst

ACK or read cycle

Figure 14. Definition of RESET timing

PCA9537

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© NXP B.V. 2021. All rights reserved.

Product data sheet

Rev. 7 — 8 September 2021

COMPANY PUBLIC

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