19/35

L6918 L6918A

INPUT CAPACITOR

The input capacitor is designed considering mainly the input rms current that depends on the duty cycle as re-

ported in figure. Considering the four phase topology, the input rms current is highly reduced comparing with

single or dual phase operation.

It can be observed that the input rms value is one half of the dual-phase equivalent input current in the worst-

case condition that happens for D=1/8, 3/8,5/8 and 7/8.

The power dissipated by the input capacitance is then equal to:

Input capacitor is designed in order to sustain the ripple relative to the maximum load duty cycle. To reach the

high rms value needed by the CPU power supply application and also to minimize components cost, the input

capacitance is realized by more than one physical capacitor. The equivalent rms current is simply the sum of

the single capacitor's rms current.

Figure 10. Input rms Current vs. Duty Cycle.

OUTPUT CAPACITOR

Since the microprocessors require a current variation beyond 100A doing load transients, with a slope in the

range of tenth A/

µs, the output capacitor is a basic component for the fast response of the power supply.

Dual phase topology reduces the amount of output capacitance needed because of faster load transient re-

sponse (switching frequency is doubled at the load connections). Current ripple cancellation due to the 180°

phase shift between the two phases also reduces requirements on the output ESR to sustain a specified voltage

ripple.

When a load transient is applied to the converter's output, for first few microseconds the current to the load is

supplied by the output capacitors. The controller recognizes immediately the load transient and increases the

duty cycle, but the current slope is limited by the inductor value.

The output voltage has a first drop due to the current variation inside the capacitor (neglecting the effect of the

ESL):

P

RM S

ESR

I

RMS

()

2

⋅

=

0.50

0.75

0.25

0.50

0.25

Single Phase

Dual Phase

4 Phase

∆V

OU T

∆I

OU T

ESR

⋅

=