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L6932D1.2 데이터시트(PDF) 7 Page - STMicroelectronics |
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L6932D1.2 데이터시트(HTML) 7 Page - STMicroelectronics |
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7 / 10 page ![]() 7/10 L6932 Loop Stability The stability of the loop is affected by the zero introduced by the output capacitor. The time constant of the zero is given by: This zero helps to increase the phase margin of the loop until the time constant is higher than some hundreds of nsec, depending also on the output voltage and current. So, using very low ESR ceramic capacitors could produce oscillations at the output, in particular when regulating high output voltages (adjustable version). To solve this issue is sufficient to add a small capacitor (e.g. 1nF to 10nF) in parallel to the high side resistor of the external divider, as shown in figure 9. Figure 9. Compensation Network Thermal Considerations Since the device is housed in a small SO(4+2+2) package the thermal issue can be the bottleneck of many ap- plications. The power dissipated by the device is given by: PDISS = (VIN - VOUT) · IOUT The thermal resistance junction to ambient of the demoboard is approximately 62°C/W. This mean that, consid- ering an ambient temperature of 60°C and a maximum junction temperature of 150°C, the maximum power that the device can handle is 1.5W. This means that the device is able to deliver a DC output current of 2A only with a very low dropout. In many applications, high output current pulses are required. If their duration is shorter than the thermal con- stant time of the board, the thermal impedance (not the thermal resistance) has to be considered. In figure 10 the thermal impedance versus the duration of the current pulse for the SO(4+2+2) mounted on board is shown. T ESR C OUT ⋅ = F ZER O 1 2 π ESR C OUT ⋅ ⋅ -------------------------------------------- = VOUT=1.2V TO 5V UP to 2A VIN=2V TO 14V C1 OUT 1 3 7 5 6 4 8 2 L6932D1.2 GND C2 IN EN ADJ R1 R2 C3 |
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