MPF0900AMMA2ES datasheet(90/205 Pages) NXP

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NXP Semiconductors

PF09

Nine-channel power management IC with advanced system safety monitoring

13 Functional blocks

13.1 Analog core and internal references

13.1.1 VANA

The PF09 uses a low-power analog supply to power various internal analog circuits. The VANA supply is

disabled during the ULPOFF, LPOFF and DFS states to reduce power consumption on those states.

The VANA supply must be decoupled externally with a 1 μF capacitor. The system, however, is not allowed to

use the supply to power external circuits, except for the scenarios where the VANA is used as the pullup voltage

for the XFAILB pin.

An undervoltage detection circuit serves as the POR threshold for the circuits powered by this regulator inside

of the PF09. When an undervoltage is detected in the VANA supply during the SYSTEM ON states, the device

will move to the Deep Fail-safe state (DFS).

An overvoltage detection is provided in the VANA regulator as part of the functional safety architecture. When

the VANA crosses the OV threshold, the VANA_OV_I interrupt bit is set and the INTB pin will be asserted low if

the interrupt is not masked.

The VANA_OV_S bit provides the real-time status of the VANA overvoltage monitor.

Symbol

Parameter

Min

Typ

Max

Unit

VANA

VANA Output Voltage

1.55

1.6

1.65

CVANA

VANA output capacitor

—

μF

VANA_OV_S

VANA overvoltage status

No OV detected

OV detected

Table 105. VANA overvoltage status

13.1.2 VDIG

The PF09 uses a low-power digital supply to power the digital circuits inside the IC. The VDIG supply is

disabled only during the ULPOFF states, to achieve the lowest power consumption in this state.

An undervoltage detection circuit serves as the POR threshold for the digital controller powered by this regulator

inside of the PF09.

An overvoltage detection is provided in the VDIG regulator as part of the functional safety architecture. When

the VDIG crosses the OV threshold, the VDIG_OV_I interrupt bit is set, and the INTB pin will be asserted low

if the interrupt is not masked. Devices targeting a higher safety integrity level featuring a dedicated digital

machine supervisor (DMS) provide a second level of protection against a VDIG_OV condition, to ensure a

proper safe reaction even if such a condition causes the main digital controller to be unresponsive.

The VDIG_OV_S bit provides the real-time status of the VDIG overvoltage monitor.

Symbol

Parameter

Min

Typ

Max

Unit

VDIG

VDIG Output Voltage

1.55

1.6

1.65

CVDIG

VDIG output capacitor

—

μF

PF09

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 1.3 — 16 December 2025

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