AD4086BBCZ datasheet(49/91 Pages) AD

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Data Sheet

AD4086

DIGITAL INTERFACE

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Rev. 0 | 49 of 91

Table 23. SPI Data Lane(s) Data Order and Pin Assignment

Serial Data Output Pin

Output Data Order

One Active SPI Lane

(SPI_LVDS_LANES = 0)

Four Active SPI Lanes

(SPI_LVDS_LANES = 1)

SDOA

Not applicable

SDO 3

SDOB

SDO 0

SDO 2

SDOC

Not applicable

SDO 1

SDOD

Not applicable

SDO 0

Data Interface CRC

To ensure the integrity of the result data, a CRC is appended

to the FIFO results. This CRC is always enabled and appended.

The computation of the result checksum is independent of that of

the configuration interface. The result is 24 bits in length and is

appended to each data result record acquired from the FIFO.

Sign Extension

When accessing the FIFO data with the SPI data interface, the

14-bit resolution of the AD4086 is not a convenient length for

interfacing with microcontroller or microprocessor hosts. To make

data access and storage simpler, the ADC result is sign extended to

24 bits. In this way, the data format aligns better with their selected

host.

GPIO PINS

The AD4086 GPIO pins are intended to simplify the development of

synchronous data acquisition applications by facilitating a simplified

state control interface between the host processor, the data con-

verter, and other related signal chain components. When configured

as an output, these GPIO pins can be assigned as an indicator of

device status, a digital control for a related signal chain component,

or a serial data lane for device configuration. In input mode, the

GPIO pins allow pin programming of converter features such as

digital filter synchronization (reset) and an external event trigger.

The desired function for each GPIO is defined by writing to the

GPIO Configuration A through GPIO Configuration C registers

(Address 0x19 through Address 0x1B), see the GPIO Configuration

A Register section through the GPIO Configuration C Register

section. The configuration for each GPIO includes an output enable

bit, an output data bit, and a function selection. The output data

bit determines the logical state of the output when the GPO data

option is selected; otherwise, the output state is determined by

the selected function, assuming the output is enabled. By default,

GPIO0 is enabled as an output, and the configuration SPI SDO

function is selected. All other GPIO outputs are disabled.

Table 25 provides a brief description of the available AD4086 GPIO

functions. Each of the GPIO pins can be configured for any of the

following functions.

Table 24. GPIO Registers Overview

Bits

Contents

GPIO_CONFIG_A

GPIO_0_EN,

GPIO_1_EN,

GPIO_2_EN,

GPIO_3_EN

Enable bits for each GPIO.

0: Configures the GPIO as an input.

1: Configures the GPIO as an output.

GPIO_CONFIG_A

GPIO_0_DATA,

GPIO_1_DATA,

GPIO_2_DATA,

GPIO_3_DATA

The corresponding GPIO_x_SEL bit for each GPIO can be set to 0111b to read or write data to that GPIO.

In this mode, GPIO_x_EN selects whether each of these data bits is read only or write only, depending on whether the GPIO is

configured as an input or an output.

When configured as an output, these bits are write only, the user can set the bits to a logic level that they need to output on the

GPIO.

When configured as an input, these bits are read only, the user can read the bits to determine the logic level input to on the GPIO.

If the corresponding GPIO_x_SEL is not set to 0111b, the GPIO_x_DATA is not valid as the GPIO is overridden with the selected

GPIO function.

GPIO_CONFIG_B

GPIO_0_SEL,

GPIO_1_SEL

Selection for the function mode of GPIO0 and GPIO1.

GPIO_CONFIG_C

GPIO_2_SEL,

GPIO_3_SEL

Selection for the function mode of GPIO2 and GPIO3.

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