2 / 8 page
CY2SSTV8575
Document #: 38-07458 Rev. **
Page 2 of 8
Pin Description
Pin
Name
I/O
Type
Description
5,6
CLK, CLK#
I
LV Differential Input
Differential Clock Input
21
FBIN#
I
Differential Input
Feedback Clock Input. Connect to FBOUT# for accessing the
PLL.
22
FBIN
I
Feedback Clock Input. Connect to FBOUT for accessing the
PLL.
2,12,15,27,30
Y(0:4)
O
Differential Outputs
Clock + Outputs
1,11,16,28,31
Y(0:4)#
O
Clock – Outputs
18
FBOUT
O
Differential Outputs
Feedback Clock Output. Connect to FBIN for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
19
FBOUT#
O
Feedback Clock Output. Connect to FBIN# for normal
operation. A bypass delay capacitor at this output will control
Input Reference/Output Clocks phase relationships.
23
OE
I
Output Enable Input. When OE is set HIGH, all Q and Q#
outputs are enabled and switch at the same frequency as CLK.
When set LOW, all Q and Q# outputs are disabled (Hi-Z) and
the PLL is powered down.
3,4,7,13,20,26,
29
VDDQ
2.5V Nominal
2.5V Power Supply for Output Clock Buffers
8AVDD
2.5V Nominal
2.5V Power Supply for PLL. When AVDD is at GND, PLL is
bypassed and CLK is buffered directly to the device outputs.
During disable (OE = 0), the PLL is powered down.
10,14,17,24,25,
32
VSS
0.0V Ground
Common Ground
9
AVSS
0.0V Analog Ground
Analog Ground
Table 1. Function Table
INPUTS
OUTPUTS
PLL
AVDD
OE
CLK
CLK#
Y
Y#
FBOUT
FBOUT#
GND
H
L
H
L
H
L
H
BYPASSED/OFF
GND
H
H
L
H
L
H
L
BYPASSED/OFF
XL
L
H
Z
Z
Z
Z
Off
XL
H
L
Z
Z
Z
Z
OFF
2.5V
H
L
H
L
H
L
H
On
2.5V
H
H
L
H
L
H
L
On
2.5V
H
< 20 MHz
< 20 MHz
Hi-Z
Hi-Z
Hi-Z
HI-Z
Off
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
