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CY7C0430BV
CY7C0430CV
Document #: 38-06027 Rev. *B
Page 13 of 37
Read Cycle[12, 13, 14, 15, 16]
Notes:
12. OE is asynchronously controlled; all other inputs (excluding MRST) are synchronous to the rising clock edge.
13. CNTLD = VIL, MKLD = VIH, CNTINC = x, and MRST = CNTRST = VIH.
14. The output is disabled (high-impedance state) by CE = VIH following the next rising edge of the clock.
15. Addresses do not have to be accessed sequentially. Note 13 indicates that address is constantly loaded on the rising edge of the CLK. Numbers are for reference
only.
16. CE is internal signal. CE = VIL if CE0 = VIL and CE1 = VIH.
Switching Waveforms (continued)
tCH2
tCL2
tCYC2
tSC
tHC
tSW
tHW
tSA
tHA
An
An+1
CLK
CE
R/W
ADDRESS
DATAOUT
OE
An+2
An+3
tSC
tHC
tOHZ
tOE
tOLZ
tDC
tCD2
tCKLZ
Qn
Qn+1
Qn+2
1 Latency
LB
UB
tSB
tHB
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