TPWM = 1/fPWM

Reserved duty cycle range for

diagnostics

PWM out

t

Duty cycle range for angle

value transmission

Figure 8

PWM interface with duty cycle range starting with a rising edge

 

As the PWM interface is an analog protocol, the rise and fall times, as well as the trigger level for the detection of the

high and low state of the signal have influence on the measured duty cycle. Therefore, an additional angle error is

introduced which varies with the measurement conditions (e.g. Rp, CW, trigger level). This error contribution is not

included in the angle error definition.

Table 18

PWM interface parameters

Parameter

Symbol

Values

Unit

Note or condition

Min.

Typ.

Max.

Data resolution -

12

-

-

bit

-

Output

frequencies

fPWM

200

-

3000

Hz

configurable in steps of 1Hz; frequency

depending rise/fall time inaccuracies result in

additional angle error

Output

frequency

tolerance

PWMfreq_tol -

-

±5

%

-

Maximum data

duty cycle range

DCdata_max 5

-

95

%

configurable, the 12 bit angle value is mapped

to this duty cycle range

High diagnostic

duty cycle

DCdiag_high 75

-

99

%

high time to period; f < 2kHz PWM frequency

(table continues...)

TLE49SR

Datasheet

5  Specific module descriptions

Datasheet

17

Rev. 1.1.1

2024-03-13