EV5424-R-00A datasheet(39/44 Pages) MPS

39 / 44 page

MP5424

– 5V POWER MANAGEMENT IC WITH I2C AND MTP

MP5424 Rev. 1.0

MonolithicPower.com

12/6/2021

MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.

PCB Layout Guidelines (19)

Efficient

PCB

layout

critical

for

stable

operation. It is recommended to use a 4-layer

board for improved performance. For the best

results, refer to Figure 17 and follow the

guidelines below:

1. Connect the input ground to the GNDx pin

using short and wide traces.

2. Connect the input capacitor to the VINx pin

using short and wide traces.

3. Ensure FB1, FB2, FB3, and FB4 are Kelvin-

connected to the buck 1, buck 2, buck 3, and

buck 4 output capacitors. Do not connect FB

directly

to the inductor’s output node.

4. Route SW away from sensitive analog areas,

such as FB1, FB2, FB3, and FB4.

C14

Buck 1

Buck 3

Buck 2

Buck 4

VIN1

VIN2

VIN3

VIN4

VIN5

SW3

SW1

SW2

SW4

PGND

AGND

VIN1

SW1

GND1

SW3

VIN2

SW2

GND2

SW4

VIN4

AVIN

AGND

LSWO/

EN1

LSW1

SCL

SDA

OUT4

VIN5

PWRON

FB2

FB4

FB3

FB1

RSTO

OUT2

OUT5

VIN3

Top Layer

Mid-Layer 1

Bottom Layer

Figure 17: Recommended PCB Layout (20)

Notes:

19) The recommended PCB layout is based on Figure 18 on page 40.

20) It is recommended to separate buck 1

’s PGND and buck 3’s PGND from buck 2’s PGND and buck ’s PGND on the top layer.

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