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CY22K7PVC-1 데이터시트(PDF) 8 Page - Cypress Semiconductor

부품명 CY22K7PVC-1
상세설명  133-MHz Spread Spectrum Clock Generator For Use With the AMD-K7짰 Processor and AMD-750 Chipset
PDF  13 Pages
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제조업체  CYPRESS [Cypress Semiconductor]
홈페이지  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY22K7PVC-1 데이터시트(HTML) 8 Page - Cypress Semiconductor

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CY22K7
Document #: 38-07333 Rev. OBS
Page 7 of 12
CY22K7 CPUCLK Driver Characteristics (Open Drain)[7]
Parameter
Description
Conditions
Min.
Typ.
Max.
Unit
VDIF
Differential Voltage
See Note 5
0.4
Vpullup (External) +
0.6
V
Vx
Differential Crossover Voltage
Vpullup is to 1.5V
550
750
950
mV
VX
Differential Crossover Voltage
Vpullup (External) = 1.4 to 1.9V
Min. = (Vpullup (External)/2) –
150 mV
Max. = (Vpullup (External)/2) +
150 mV
550
750
1100
mV
Electrical Characteristics Over the Operating Range
Parameter
Description
Test Conditions
Min. Max. Unit
CY22K7 Switching Characteristics[6, 7] Over the Operating Range @ 100 MHz
Parameter
Output
Description
Test Conditions
Min.
Typ.
Max.
Unit
t1
All
Output Duty Cycle
t1A/t1B[8]
45
55
%
t2
CPU
Rising Edge Rate
At Output of CY22K7 CPU±
1.0
V/ns
t2
CPU
Rising Edge Rate
As measured at Observation Point in
Figure 1
0.4
V/ns
t2
PCI
Rise Time
Between 0.4V and 2.4V
2.0
ns
t2
SDRAM_OUT Rise Time
Between 0.4V and 2.4V
2.0
ns
t2
AGP
Rise Time
Between 0.4V and 2.4V
0.4
2.0
ns
t2
USB, REF
Rise Time
Between 0.4V and 2.4V
4.0
ns
t3
CPU
Falling Edge Rate
At Output of CY22K7 CPU±
1.0
V/ns
t3
CPU
Falling Edge Rate
As measured at Observation Point in
Figure 1
0.4
V/ns
t3
PCI
Fall Time
Between 2.4V and 0.4V
2.0
ns
t3
SDRAM_OUT Fall Time
Between 2.4V and 0.4V
2.0
ns
t3
AGP
Fall Time
Between 2.4V and 0.4V
0.4
2.0
ns
t3
USB, REF
Fall Time
Between 2.4V and 0.4V
4.0
ns
t4
CPU, PCI
CPU-PCI Offset
Load shown in Figure 1 & Figure 2
500
700
ps
t4
CPU, SDRAM CPU-SDRAM Skew
Load shown in Figure 1 & Figure 2
500
700
ps
t4
CPU, AGP
CPU-AGP Skew
Load shown in Figure 1 & Figure 2
1000
ps
t4
CPU, CPU
CPU-CPU Skew
Load shown in Figure 1
250
ps
t4
PCI, PCI
PCI-PCI Skew
Load shown in Figure 2
500
ps
t5
CPU
Cycle-Cycle Clock Jitter
Measured at VX, t5A–t5B
250
ps
Notes:
5.
VDIF specifies the minimum input differential voltages (VTR – VCP) required for switching, where VTR is the ‘true’ input level and VCP is the ‘complement’ input
level.
6.
All parameters specified with loaded outputs.
7.
All parameters for CPU are measured at observation point shown in Figure 1 on page 10 and parameters for PCI, SDRAM & AGP are measured at observation
point shown in Figure 2 on page 11 unless otherwise mentioned.
8.
For 133-MHz Output Duty Cycle will be guaranteed at 40% Min., 60% Max.



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