AD7357

Preliminary Technical Data

Rev. PrD | Page 14 of 17

mode is more suited to applications where a series of

conversions performed at a relatively high throughput rate are

followed by a long period of inactivity and thus, power-down.

When the AD7357 is in full power-down, all analog circuitry is

powered down. Full power-down is entered in a similar way as

partial power-down, except the timing sequence shown in

Figure 15 must be executed twice. The conversion process must

be interrupted in a similar fashion by bringing CS high

falling edge of SCLK. The device enters partial power down at

this point.

To reach full power-down, the next conversion cycle must be

interrupted in the same way, as shown in Figure 17. Once CS

has been brought high in this window of SCLKs, the part

completely powers down.

Note that it is not necessary to complete the 16 SCLKs once CS

has been brought high to enter a power-down mode.

To exit full power-down mode and power-up the AD7357, a

dummy conversion is performed, as when powering up from

partial power-down. One the falling edge of CS , the device

begins to power up, as long as CS is held low until after the

elapse before a conversion can be initiated, as shown in Figure

18.

SCLK

CS

INVALID DATA

VALID DATA

110

14

14

1

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY

POWERED UP; SEE

POWER-UP TIMES

SECTION.

Figure 16. Exiting Partial Power-Down Mode

THREE-STATE

110

14

2

SCLK

CS

THREE-STATE

110

14

2

INVALID DATA

INVALID DATA

THE PART BEGINS

TO POWER UP.

THE PART ENTERS

PARTIAL POWER DOWN.

THE PART ENTERS

FULL POWER DOWN.

Figure 17. Entering Full Power-Down Mode

SCLK

INVALID DATA

VALID DATA

1

10

14

14

1

THE PART BEGINS

TO POWER UP.

THE PART IS FULLY POWERED UP,

SEE POWER-UP TIMES SECTION.

CS

Figure 18. Exiting Full Power-Down Mode