3.3V 125-MHz 8-Output Zero Delay Buffer
CY29653
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
, CA 95134
•
408-943-2600
Document #: 38-07477 Rev. *C
Revised April 13, 2004
Features
• Output frequency range: 25 MHz to 125 MHz
• Input frequency range (
÷4): 35 MHz to 125 MHz
• Input frequency range (
÷8): 25 MHz to 62.5 MHz
• 30 ps typical peak cycle-to-cycle jitter
• 30 ps typical out-to-output skew
• 3.3V operation
• Eight Clock outputs: Drive up to 16 clock lines
• One feedback output
• LVPECL reference clock input
• Phase-locked loop (PLL) bypass mode
• Spread Aware™
• Output enable/disable
• Pin-compatible with MPC9653 and MPC953
• Industrial temperature range: –40°C to +85°C
• 32-pin 1.0-mm TQFP package
Description
The CY29653 is a low-voltage high-performance 125-MHz
PLL-based zero delay buffer designed for high-speed clock
distribution applications. The CY29653 features an LVPECL
reference clock input and provides eight outputs plus one
feedback output. VCO output divides by four or eight per
VCO_SEL
setting
(see
the
Function
Table).
Each
LVCMOS-compatible output can drive 50
Ω series- or
parallel-terminated transmission lines. For series-terminated
transmission lines, each output can drive one or two traces
giving the device an effective fanout of 1:16.
The PLL is ensured stable given that the VCO is configured to
run between 140 MHz to 500 MHz. This allows a wide range
of output frequencies from 25 MHz to 125 MHz. For normal
operation, the external feedback input, FB_IN, is connected to
the feedback output, FB_OUT. The internal VCO is running at
multiples of the input reference clock set by the feedback
divider (see the Frequency Table).
When PLL_EN is LOW, PLL is bypassed and the reference
clock directly feeds the output dividers. This mode is fully static
and the minimum input clock frequency specification does not
apply. When BYPASS# is set LOW, PLL and output dividers
are bypassed resulting in a 1:9 LVPECL to LVCMOS high
performance fanout buffer. For normal PLL operation both
PLL_EN and BYPASS# are set HIGH.
Block Diagram
Pin Configuration
Phase
Detector
LPF
VCO
200-500MHz
÷4
÷2
PECL_CLK
PECL_CLK#
FB_IN
VCO_SEL
BYPASS#
MR/OE#
PLL_EN
FB_OUT
Q(0:6)
Q7
CY 2 965 3
Q1
VDD Q
Q2
VS S
Q3
VDD Q
Q4
VS S
AVD D
FB _IN
NC
NC
NC
NC
AV SS
PE CL _C L K
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
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