TMP512 datasheet(21/60 Pages) TI2

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Byte: 1010 1010 (AAh)

MSB

SCL

SDA

Bit

LSB

ACK

SDA line is stable while SCL line is high

Figure 7-11. Bit Transfer

7.5.3 Serial Bus Address

The serial bus address consists of a 7-bit value, followed by an 8th bit that indicates whether the controller is

issuing a Read or a Write command. If the 8th bit is a logic '0', the controller is writing data to the target device. If

the 8th bit is a logic '1', the controller is reading data from the target device.

The 7-bit serial bus address for TMP4719 is 4Dh (1001101b).

7.5.4 Bus Transactions

Registers are locations in the memory of the target that contain information, including configuration information

and sampled data to send back to the controller. The controller must write information to these registers to

instruct the target device to perform a task.

7.5.4.1 Writes

To write on the I2C bus, the controller sends a START condition on the bus with the address of the target, as well

as the last bit (the R/W bit) set to 0, which signifies a write. The target acknowledges, letting the controller know

the target is ready. After this, the controller starts sending the register pointer followed by the register data to the

target. The controller terminates the transmission with a STOP condition.

Writes to read-only registers or register locations outside of the register map are ignored, and the TMP4719-Q1

performs a NACK to the data that the controller tries to send.

Figure 7-12 shows an example of writing a single-byte write communication. TMP4719-Q1 does not support

multiple-byte writes.

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TMP4719-Q1

SLVSJS0 – DECEMBER 2025

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TMP512 데이터시트(PDF) 21 Page - Texas Instruments