TMP512 datasheet(8/63 Pages) TI2

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6.6 I2C Interface Timing

minimum and maximum specifications are over –40 °C to 125 °C and VDD = 1.62 V to 5.5 V (unless otherwise noted)(1)

STANDARD MODE

FAST MODE

UNIT

MIN

MAX

MIN

MAX

f(SCL)

SCL operating frequency(2)

100

400

kHz

t(BUF)

Bus free time between STOP and START condition

4.7

–

1.3

–

µs

t(HDSTA)

Hold time after repeated START condition. After this

period, the first clock is generated.

4.0

–

0.6

–

µs

t(SUSTA)

Repeated START condition setup time

4.7

–

0.6

–

µs

t(SUSTO)

STOP condition setup time

4.0

–

0.6

–

µs

t(HDDAT)

Data hold time(3)

3450

900

t(SUDAT)

Data setup time

250

–

100

–

t(LOW)

SCL clock LOW period

4.7

–

1.3

–

µs

t(HIGH)

SCL clock HIGH period

4.0

–

0.6

–

µs

t(VDAT)

Data valid time (data response time)(4)

–

3.45

–

0.9

µs

Clock and data fall time(5)

–

300

20 ×

(VDD / 5.5 V)

300

Clock and data rise time(5)

–

1000

300

ttimeout

Timeout (SCL = GND)

(1)

The controller and target have the same I/O supply value. Values are based on statistical analysis of samples tested during initial

release.

(2)

Device is equipped with a 50-ns spike filter on both SCL and SDA lines. The filter allows the device to be used alongside I3C devices

without impacting the communication.

(3)

The maximum t(HDDAT) can be 3.45 µs and 0.9 µs for Standard Mode and Fast Mode, but must be less than the maximum of t(VDAT) by

a transition time.

(4)

t(VDAT) = time for data signal from SCL LOW to SDA output (HIGH to LOW, depending on which is worse).

(5)

Device is not sensitive to rise and fall time. Violation of rise and fall time does not lead to communication failure.

SCL

SDA

(LOW)

(HDSTA)

(HDDAT)

(BUF)

(SUDAT)

(HIGH)

(SUSTA)

(SUSTO)

Figure 6-1. Two-Wire Timing Diagram

TMP4719

SBOSAJ7A – OCTOBER 2025 – REVISED DECEMBER 2025

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