W144
Document #: 38-07153 Rev. *B
Page 11 of 14
SDRAM Clock Outputs, SDRAM, SDRAM0:11 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6 MHz
CPU = 100.2 MHz
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
tP
Period
Measured on rising edge at 1.5V
30
–
–
30
–
–
ns
tH
High Time
Duration of clock cycle above 2.4V,
at min. edge rate (1.5V/ns)
5.6
–
–
3.3
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V,
at min. edge rate (1.5V/ns
5.3
–
–
3.1
–
–
ns
tR
Output Rise Edge
Rate
Measured from 0.4V to 2.4V
1.5
–
4
1.5
–
4
V/ns
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
1.5
–
4
1.5
–
4
V/ns
tPLH
Prop Delay LH
Input edge rate faster than 1V/ns
1
–
5
1
–
5
ns
tPHL
Prop Delay HL
Input edge rate faster than 1 V/ns
1
–
5
1
–
5
ns
tD
Duty Cycle
Measured on rising and falling edge
at 1.5V,at min. edge rate (1.5 V/ns)
45
–
55
45–55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V.
Maximum difference of cycle time
between two adjacent cycles.
––
250
–
–
250
ps
tSK
Output Skew
Measured on rising edge at 1.5V
–
–
250
–
–
250
ps
tO
CPU to PCI Clock
Skew
Covers all CPU/PCI outputs.
Measured on rising edge at 1.5V.
CPU leads PCI output.
1.5
–
4
1.5
–
4
ns
fST
Frequency
Stabilization from
Power-up (cold start)
Assumes full supply voltage
reached within 1 ms from power-up.
Short cycles exist prior to frequency
stabilization.
––
3
–
–
3
ms
Zo
AC Output
Impedance
Average value during switching
transition. Used for determining
series termination value.
–30
–
–
30
–
Ω
PCI Clock Outputs, PCI_F and PCI1:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
CPU = 66.6/100.2 MHz
Unit
Min.
Typ.
Max.
tP
Period
Measured on rising edge at 1.5V
29.9
–
–
ns
tH
High Time
Duration of clock cycle above 2.4V
12.0
–
–
ns
tL
Low Time
Duration of clock cycle below 0.4V
12.0
–
–
ns
tR
Output Rise Edge Rate
Measured from 0.4V to 2.4V
1
–
4
V/ns
tF
Output Fall Edge Rate
Measured from 2.4V to 0.4V
1
–
4
V/ns
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
–
55
%
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two
adjacent cycles.
––
250
ps
tSK
Output Skew
Measured on rising edge at 1.5V
–
–
500
ps
tO
CPU to PCI Clock Skew
Covers all CPU/PCI outputs. Measured on
rising edge at 1.5V. CPU leads PCI output.
1.5
–
4.0
ns
fST
Frequency Stabilization
from Power-up (cold start)
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior
to frequency stabilization.
––
3.0
ms
Zo
AC Output Impedance
Average value during switching transition.
Used for determining series termination
value.
–30–
Ω
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