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TAS5706PAPRG4 데이터시트(PDF) 28 Page - Texas Instruments

부품명 TAS5706PAPRG4
상세설명  20-W Stereo Digital Audio Power Amplifier with EQ and DRC
PDF  62 Pages
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제조업체  TI [Texas Instruments]
홈페이지  http://www.ti.com
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TAS5706PAPRG4 데이터시트(HTML) 28 Page - Texas Instruments

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Right-Justified
23
22
SCLK
32Clks
LRCLK
LeftChannel
24-BitMode
1
20-BitMode
16-BitMode
15
14
MSB
LSB
SCLK
32Clks
RightChannel
2-ChannelRight-Justified(SonyFormat)StereoInput
T0034-03
19
18
1
19
18
1
0
0
0
15
14
15
14
23
22
1
15
14
MSB
LSB
19
18
1
19
18
1
0
0
0
15
14
15
14
TAS5706
SLOS550A – DECEMBER 2007 – REVISED DECEMBER 2007
Right-justified (RJ) timing uses LRCLK to define when the data being transmitted is for the left channel and when
it is for the right channel. LRCLK is high for the left channel and low for the right channel. A bit clock running at
32, 48, or 64
× f
S is used to clock in the data. The first bit of data appears on the data 8 bit-clock periods (for
24-bit data) after LRCLK toggles. In RJ mode the LSB of data is always clocked by the last bit clock before
LRCLK transitions. The data is written MSB first and is valid on the rising edge of bit clock. The DAP masks
unused leading data bit positions.
Figure 36. Right Justified 64-fS Format
28
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Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TAS5706



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