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M28W640HCT 데이터시트(PDF) 18 Page - Numonyx B.V

부품명 M28W640HCT
상세설명  64 Mbit (4 Mb x 16, boot block) 3 V supply Flash memory
PDF  72 Pages
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제조업체  NUMONYX [Numonyx B.V]
홈페이지  http://www.numonyx.com
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M28W640HCT 데이터시트(HTML) 18 Page - Numonyx B.V

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Command interface
M28W640HCT, M28W640HCB
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Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the erase
operation is aborted, the block must be erased again.
During erase operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command, all other commands will be ignored. Typical Erase
times are given in Table 8: Program, Erase times and Program/Erase endurance cycles.
See Appendix C, Figure 19: Erase flowchart and pseudocode, for a suggested flowchart for
using the Erase command.
4.6
Program command
The memory array can be programmed word-by-word. Two bus write cycles are required to
issue the Program command:
●
The first bus cycle sets up the Program command.
●
The second latches the address and the data to be written and starts the
Program/Erase controller.
During program operations the memory will accept the Read Status Register command and
the Program/Erase Suspend command. Typical Program times are given in Table 8:
Program, Erase times and Program/Erase endurance cycles.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 15: Program flowchart and pseudocode, for the flowchart for using
the Program command.
4.7
Double Word Program command
This feature is offered to improve the programming throughput, writing a page of two
adjacent words in parallel.The two words must differ only for the address A0. Programming
should not be attempted when VPP is not at VPPH.
Three bus write cycles are necessary to issue the Double Word Program command:
●
The first bus cycle sets up the Double Word Program command
●
The second bus cycle latches the address and the data of the first word to be written
●
The third bus cycle latches the address and the data of the second word to be written
and starts the Program/Erase controller.
Read operations output the Status Register content after the programming has started.
Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the
program operation is aborted, the block containing the memory location must be erased and
reprogrammed.
See Appendix C, Figure 16: Double Word Program flowchart and pseudocode for the
flowchart for using the Double Word Program command.



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