LIS3LV02DL datasheet(21/48 Pages) STMICROELECTRONICS

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LIS3LV02DL

Application hints

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Application hints

Figure 5.

LIS3LV02DL electrical connection

The device core is supplied through Vdd line while the I/O pads are supplied through

Vdd_IO line. Power supply decoupling capacitors (100 nF ceramic, 10

µF Al) should be

placed as near as possible to the pin 13 of the device (common design practice).

All the voltage and ground supplies must be present at the same time to have proper

behavior of the IC (refer to Figure 7). It is possible to remove Vdd maintaining Vdd_IO

without blocking the communication busses. In this condition the measurement chain is

powered off.

The functionality of the device and the measured acceleration data is selectable and

accessible through the I2C/SPI interface.When using the I2C, CS must be tied high while

SDO must be left floating. Refer to dedicated application note for further information on

device usage.

The functions, the trasholds and the timing of the interrupt pin (INT) can be completely

programmed by the user through the I2C/SPI interface.

4.1

Soldering Information

The LGA-16 package is compliant with the ECOPACK®, RoHS and “Green” standard.

It is qualified for soldering heat resistance according to JEDEC J-STD-020C.

Leave “Pin 1 Indicator” unconnected during soldering.

Land pattern and soldering recommendations are available at www.st.com/mems.

DIRECTION OF THE

DETECTABLE

ACCELERATIONS

Vdd_IO

10uF

Vdd

Digital signal from/to signal controller.Signal’s levels are defined by proper selection of Vdd_IO

100nF

GND

LIS3LV02DL

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