MPC8260 UPM Timing Diagram, Rev. 2

10

Freescale Semiconductor

UPM Timings

Figure 5 shows the UPM with two consecutive WAEN.

Figure 5. UPM with Two Consecutive WAEN

CLKIN

ADDR

DATA

PSDVAL

D0

CS

PGPLx

BS

addr

Note:

00: 08ea a800

01: 00a0 0000

02: 00a0 1000 // WAEN=1

03: 00a0 1000 // WAEN=1

04: 01b5 4405

what happens if only one WAEN is set.

UPWAIT goes active half a cycle after CS is active, the first WAEN that has an effect is at RAM address 02 for

a read. Even if WAEN values of 00 and 01 are configured, the UPM does not wait because UPWAIT has not

arrived yet due to delay.

00

01

02

03

03

03

03

03

03

UPWAIT

internal

UPWAIT

03

04