CE6313 datasheet(6/24 Pages) INTEL

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CE6313

Data Sheet

Intel Corporation

Additional Features

• 2-wire bus microprocessor interface

• All-digital clock and carrier recovery

• On-chip PLL clock generation using a low cost

10 to 16 MHz crystal (or external clock)

• 3.3/1.8 V operation

• 64 pin LQFP package

• Low external component count

• Commercial temperature range 0 to 70°C

• External MPEG clock option

Demodulator

• BPSK or QPSK programmable

• Optional fast acquisition mode for low symbol

rates

Viterbi

• Programmable decoder rates 1/2, 2/3, 3/4, 5/6,

6/7, 7/8

• Automatic spectrum resolution of IQ phase

• Constraint length k = 7

• Trace back depth 128

• Extensive SNR and BER monitors

De-Interleaver

• Compliant with DVB and DSS standards

Reed-Solomon

• (204, 188) for DVB and (146,130) for DSS

• Reed-Solomon bit-error-rate monitor to indicate

Viterbi performance

De-Scrambler

• EBU specification de-scrambler for DVB mode

Outputs

• MPEG transport parallel & serial output

• Three output clocking modes for maximum

flexibility

• Integrated MPEG2 TEI bit processing for DVB only

Application Support

• Windows based evaluation software

• ANSI-C compliant software

• A full DVB-S front-end satellite tuner reference

design kit is available for evaluation, based on the

schematic below (Figure 4). Intel reference CE9541

CE6313 데이터시트(PDF) 6 Page - Intel Corporation

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