W77C32 datasheet(49/78 Pages) WINBOND

49 / 78 page

W77C32/W77C032A

Publication Release Date: February 1, 2007

- 49 -

Revision A8

The processor responds to a valid interrupt by executing an LCALL instruction to the appropriate

service routine. This may or may not clear the flag which caused the interrupt. In case of Timer

interrupts, the TF0 or TF1 flags are cleared by hardware whenever the processor vectors to the

appropriate timer service routine. In case of external interrupt, INT0 and INT1, the flags are cleared

only if they are edge triggered. In case of Serial interrupts, the flags are not cleared by hardware. In

the case of Timer 2 interrupt, the flags are not cleared by hardware. Watchdog timer interrupt flag

WDIF have to be cleared by software. The hardware LCALL behaves exactly like the software LCALL

instruction. This instruction saves the Program Counter contents onto the Stack, but does not save the

Program Status Word PSW. The PC is reloaded with the vector address of that interrupt which caused

the LCALL. These vector address for the different sources are as follows.

Table 8. Vector locations for interrupt sources

SOURCE

VECTOR ADDRESS

SOURCE

VECTOR ADDRESS

Timer 0 Overflow

000Bh

External Interrupt 0

0003h

Timer 1 Overflow

001Bh

External Interrupt 1

0013h

Timer 2 Interrupt

002Bh

Serial Port

0023h

External Interrupt 2

0043h

Serial Port 1

003Bh

External Interrupt 4

0053h

External Interrupt 3

004Bh

Watchdog Timer

0063h

External Interrupt 5

005Bh

The vector table is not evenly spaced; this is to accommodate future expansions to the device family.

Execution continues from the vectored address till an RETI instruction is executed. On execution of

the RETI instruction the processor pops the Stack and loads the PC with the contents at the top of the

stack. The user must take care that the status of the stack is restored to what is was after the

hardware LCALL, if the execution is to return to the interrupted program. The processor does not

notice anything if the stack contents are modified and will proceed with execution from the address put

back into PC. Note that a RET instruction would perform exactly the same process as a RETI

instruction, but it would not inform the Interrupt Controller that the interrupt service routine is

completed, and would leave the controller still thinking that the service routine is underway.

11.3 Interrupt Response Time

The response time for each interrupt source depends on several factors, such as the nature of the

interrupt and the instruction underway. In the case of external interrupts INT0 to INT5 , they are

sampled at C3 of every machine cycle and then their corresponding interrupt flags Iex will be set or

reset. The Timer 0 and 1 overflow flags are set at C3 of the machine cycle in which overflow has

occurred. These flag values are polled only in the next machine cycle. If a request is active and all

three conditions are met, then the hardware generated LCALL is executed. This LCALL itself takes

four machine cycles to be completed. Thus there is a minimum time of five machine cycles between

the interrupt flag being set and the interrupt service routine being executed.

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