Page 9 of 15

www.irf.com

12/22/2007

Data Sheet No. PD60322

iP2004

Internal Block Diagram

MOSFET

Driver with

dead time

control

V

IN

V

SW

P

GND

V

DD

PWM

ENABLE

NC

V

SWS1

V

SWS2

1

2

6

3

4

5

7

89

P

GND

10

Figure 12 Internal Block Diagram

Pin Description

Pin Number

Pin Name

Description

1

NC

No Connect. This pin is not for electrical connection

2

ENABLE

When set to logic level high, internal circuitry of the device is enabled. When

set to logic level low, the Control and Synchronous FETs are turned off.

3

PWM

TTL level input to MOSFET drivers. When PWM is HIGH, the Control FET is

on and the Sync FET is off. When PWM is LOW, the Sync FET is on and the

Control FET is off.

4

Supply voltage to internal circuitry.

5

Voltage Switching Node – pin connection to the output inductor.

6, 10

PGND

Power Ground

7

Input voltage pin. Connect input capacitors close to this pin.

8

9