21 / 44 page
Data Sheet #: TM084
Page 21 of 44
Rev: P02
Date: 12/5/06
© Copyright 200
6 The Connor-Winfield Corp. All Rights Reserved Specifications subject to change without notice
STC4130
Synchronous Clock for SETS
Data Sheet
Intel Bus
In Intel mode, the device will interface to 80x86 type processors. The BUS_CS, BUS_WRB, BUS_RDB,
BUS_A(6-0), BUS_AD(7-0), and BUS_RDY pins are used, corresponding to CS, WRB, RDB, A, AD, and RDY,
respectively. Timing is as follows:
Figure 13: Intel Bus Read Timing
Table 8: Intel Bus Read Timing
tRDYd2
RDY high-z delay after CS high
7
nS
Symbol
Description
Min
Max
Unit
tRDBs
Read setup time
0
nS
tRDB
Read low time
40
nS
tRDBh
Read hold time
0
nS
tRDB1
Time between consecutive reads
50
nS
tAs
Address setup
10
nS
tAh
Address hold
0
nS
tDd1
Data valid delay from RDB high
50
nS
tDd2
Data high-z delay from RDB high
10
nS
tRDYd1
CS low to RDY high delay
13
nS
Symbol
Description
Min
Max
Unit
CS
tRDBs
tDd1
WRB
A
AD
RDY
tRDB
tAs
tAh
Address
Data
tDd2
tRDYd2
tRDYd3
tRDYh
tRDY
RDB
tRDB1
tRDBh
tRDYd1
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
