STA333W datasheet(20/42 Pages) STMICROELECTRONICS

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STA333W

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7.1

Configuration registers (0x00 - 0x05)

7.1.1

Configuration register A (address 0x00)

Master clock select

The STA333W will support sample rates of 32 kHz, 44.1 kHz, 48 KHz, 88.2 kHz, 96 kHz,

176.4 kHz, and 192 kHz. Therefore the internal clock will be:

32.768 MHz for 32 kHz

45.1584 MHz for 44.1 kHz, 88.2 kHz, and 176.4 kHz

49.152 MHz for 48 kHz, 96 kHz, and 192 kHz

The external clock frequency provided to the XTI pin must be a multiple of the input sample

frequency (fs).

The relationship between the input clock and the input sample rate is determined by both

the MCSx and the IR (input rate) register bits. The MCSx bits determine the PLL factor

generating the internal clock and the IR bit determines the oversampling ratio used

internally.

FDRB

TWAB

TWRB

IR1

IR0

MCS2

MCS1

MCS0

1100

011

Table 8.

Master clock select

Bit

R/W

RST

Name

Description

0R/W

1MCS0

Master clock select: Selects the ratio between the

input I2S sample frequency and the input clock.

1R/W

1MCS1

2R/W

0MCS2

Table 9.

MCS bits

Input sample rate

fs (kHz)

MCS(2..0)

101

100

011

010

001

000

32, 44.1, 48

576 fs

128 fs

256 fs

384 fs

512 fs

768 fs

88.2, 96

64 fs

128 fs

192 fs

256 fs

384 fs

176.4, 192

32 fs

64 fs

96 fs

128 fs

192 fs

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