ST7FOXF1 datasheet(65/226 Pages) STMICROELECTRONICS

65 / 226 page

ST7FOXF1, ST7FOXK1, ST7FOXK2

Power saving modes

65/226

Figure 26.

Active-halt mode flowchart

This delay occurs only if the MCU exits Active-Halt mode by means of a RESET.

Peripherals clocked with an external clock source can still be active.

Only the Lite timer RTC and AT timer interrupts can exit the MCU from Active-Halt mode.

Before servicing an interrupt, the CC register is pushed on the stack. The I bit of the CC register is set

during the interrupt routine and cleared when the CC register is popped.

8.4.2

Halt mode

The Halt mode is the lowest power consumption mode of the MCU. It is entered by

executing the HALT instruction when active halt mode is disabled.

The MCU can exit Halt mode on reception of either a specific interrupt (seeTable 17:

ST7FOXF1/ST7FOXK1 Interrupt mapping) or a Reset. When exiting Halt mode by means of

a Reset or an interrupt, the main oscillator is immediately turned on and the 256 CPU cycle

delay is used to stabilize it. After the start up delay, the CPU resumes operation by servicing

the interrupt or by fetching the Reset vector which woke it up (see Figure 28).

When entering Halt mode, the I bit in the CC register is forced to 0 to enable interrupts.

Therefore, if an interrupt is pending, the MCU wakes immediately.

In Halt mode, the main oscillator is turned off causing all internal processing to be stopped,

including the operation of the on-chip peripherals. All peripherals are not clocked except the

ones which get their clock supply from another clock generator (such as an external or

auxiliary oscillator).

The compatibility of Watchdog operation with Halt mode is configured by the “WDGHALT”

option bit of the option byte. The HALT instruction when executed while the Watchdog

system is enabled, can generate a Watchdog Reset (see Section 13.1: Option bytes for

more details).

HALT INSTRUCTION

RESET

INTERRUPT 3)

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR

PERIPHERALS 2)

IBIT

OFF

X 4)

CPU

OSCILLATOR

PERIPHERALS

IBITS

X 4)

256 CPU CLOCK CYCLE

DELAY

(Active Halt enabled)

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