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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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ST7FOXK2 데이터시트(PDF) 177 Page - STMicroelectronics |
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ST7FOXK2 데이터시트(HTML) 177 Page - STMicroelectronics |
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177 / 226 page  ST7FOXF1, ST7FOXK1, ST7FOXK2 On-chip peripherals 177/226 Data register High (ADCDRH) Reset value: xxxx xxxx (xxh) Bits 7:0 = D[9:2] MSB of Analog Converted Value ADC Control/data register Low (ADCDRL) Reset value: 0000 00xx (0xh) Bits 7:4 = Reserved. Forced by hardware to 0. Bit 3 = SLOW Slow mode bit This bit is set and cleared by software. It is used together with the SPEED bit in the ADCCSR register to configure the ADC clock speed as shown on the table below. Bit 2 = Reserved. Forced by hardware to 0. Bits 1:0 = D[1:0] LSB of Analog Converted value 7 0 D9 D8 D7 D6 D5 D4 D3 D2 Read only 7 0 0000 SLOW 0 D1 D0 Read/write Table 56. Configuring the ADC clock speed fADC (1) 1. The maximum allowed value of fADC is 4 MHz (see Section 12.11 on page 209) SLOW SPEED fCPU/2 0 0 fCPU 01 fCPU/4 1 x Table 57. ADC register mapping and reset values Address (Hex.) Register label 76 5 4 3 2 1 0 0036h ADCCSR Reset Value EOC 0 SPEED 0 ADON 0 0 0 CH3 0 CH2 0 CH1 0 CH0 0 0037h ADCDRH Reset Value D9 x D8 x D7 x D6 x D5 x D4 x D3 x D2 x 0038h ADCDRL Reset Value 0 0 0 0 0 0 0 SLOW 0 0 D1 x D0 x |
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