| 전자부품 데이터시트 검색엔진 |
|
ST7FOXK2 데이터시트(PDF) 196 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST7FOXK2 데이터시트(HTML) 196 Page - STMicroelectronics |
|
196 / 226 page ![]() Electrical characteristics ST7FOXF1, ST7FOXK1, ST7FOXK2 196/226 Figure 83. SPI slave timing diagram with CPHA=0 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. Figure 84. SPI slave timing diagram with CPHA=1 1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD 2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has its alternate function capability released. In this case, the pin status depends on the I/O port configuration. SS INPUT CPHA=0 MOSI INPUT MISO OUTPUT CPHA=0 tc(SCK) tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) tv(SO) ta(SO) tsu(SI) th(SI) MSB OUT MSB IN BIT6 OUT LSB IN LSB OUT see note 2 CPOL=0 CPOL=1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 BIT1 IN SS INPUT CPHA=1 MOSI INPUT MISO OUTPUT CPHA=1 tw(SCKH) tw(SCKL) tr(SCK) tf(SCK) ta(SO) tsu(SI) th(SI) MSB OUT BIT6 OUT LSB OUT see CPOL=0 CPOL=1 tsu(SS) th(SS) tdis(SO) th(SO) see note 2 note 2 tc(SCK) HZ tv(SO) MSB IN LSB IN BIT1 IN |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |