| 전자부품 데이터시트 검색엔진 |
|
STR71XF 데이터시트(PDF) 45 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STR71XF 데이터시트(HTML) 45 Page - STMicroelectronics |
|
45 / 78 page ![]() STR71xF Electrical parameters 45/78 Table 22. PLL2 characteristics Symbol Parameter Test conditions Value Unit Min Typ Max fPLLCLK2 PLL multiplier output clock 140 MHz fPLL2 PLL input clock FREF_RANGE = 0 1.5 3.0 MHz FREF_RANGE = 1 3.0 5 MHz tLOCK2 PLL lock time FREF_RANGE = 0 Stable Input Clock Stable V33IOPLL, V18 300 µs FREF_RANGE = 1 Stable Input Clock Stable V33IOPLL, V18 600 µs ∆tJITTER2 PLL jitter (peak to peak) tPLL = 4 MHz, MX[1:0]=’11’ Global Output division = 32 (Output Clock = 2 MHz) 0.7 2 ns Table 23. Low-power mode wakeup timing Symbol Parameter Typ Unit tWULPWFI Wakeup from LPWFI mode 26(1) 1. Clock selected is CK2_16, Main VReg OFF and Flash in power-down µs tWUSTOP Wakeup from STOP mode 2048 CLK Cycles (2) 2. The CLK clock is derived from the external oscillator. tWUSTBY Wakeup from STANDBY mode 2048 CLK Cycles + 8 CLK2 Cycles(3) 3. Refer to Figure 7. Reset General Timing in the STR71xF Reference Manual (UM0084) Cycles |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |