M29W400B datasheet(21/34 Pages) STMICROELECTRONICS

21 / 34 page

Symbol

Alt

Parameter

M29W400T / M29W400B

Unit

-120

-150

VCC = 2.7V to 3.6V

Min

Max

Min

Max

tAVAV

tWC

Address Valid to Next Address Valid

120

150

tWLEL

tWS

Write Enable Low to Chip Enable Low

tELEH

tCP

Chip Enable Low to Chip Enable High

tDVEH

tDS

Input Valid to Chip Enable High

tEHDX

tDH

Chip Enable High to Input Transition

tEHWH

tWH

Chip Enable High to Write Enable High

tEHEL

tCPH

Chip Enable High to Chip Enable Low

tAVEL

tAS

Address Valid to Chip Enable Low

tELAX

tAH

Chip Enable Low to Address Transition

tGHEL

Output Enable High Chip Enable Low

tVCHWL

tVCS

VCC High to Write Enable Low

µs

tEHGL

tOEH

Chip Enable High to Output Enable Low

tPHPHH

(1,2)

tVIDR

RP Rise TIme to VID

500

tPLPX

tRP

RP Pulse Width

500

tEHRL

(1)

tBUSY

Program Erase Valid to RB Delay

tPHWL

(1)

tRSP

RP High to Write Enable Low

µs

Notes: 1. Sample only, not 100% tested.

2. This timing is for Temporary Block Unprotection operation.

Table 16B. Write AC Characteristics, Chip Enable Controlled

(TA = 0 to 70

°C, –20 to 85°C or –40 to 85°C)

Erase Resume (ER) Instruction. If an Erase Sus-

pend instruction was previously executed, the

erase operation may be resumed by giving the

command 30h, at any address, and without any

Coded cycles.

POWER SUPPLY

Power Up

The memory Command Interfaceis reset on power

up to Read Array. Either E or W must be tied to VIH

during Power Up to allow maximum security and

the possibility to write a command on the first rising

edge of E and W. Any write cycle initiation is

blocked when Vcc is below VLKO.

Supply Rails

Normal precautions must be taken for supply volt-

age decoupling; each device in a system should

have the VCC rail decoupled with a 0.1

µF capacitor

close to the VCC and VSS pins. The PCB trace

widths should be sufficient to carry the VCC pro-

gram and erase currents required.

21/34

M29W400T, M29W400B

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